Low Power, Low Cost CPLDs 

The ispMACH 4000ZE CPLD family is ideal for ultra low-power, high-volume portable applications. Based on Lattice’s popular low power ispMACH® 4000Z CPLD family architecture, the second-generation ispMACH 4000ZE offers typical standby current as low as 10µA; ultra-small, space saving 0.4mm pitch Ball Grid Array packages; 3.3V, 2.5V, and 1.8V I/O standards support; and 5-volt tolerant I/Os.

• Key Features
• Device Selection Guide
• Reference Designs and Development Kits

• Ultra Low Power CPLD
  • Standby current as low as 10µA (typical)
  • 1.8V core; Operational down to 1.6V V_CC  low dynamic power
  • Lower dynamic power by selectively disabling inputs with Power Guard
  • Reduce system power with per pin pull-up, pull-down or bus keeper control
  • Superior solution for power sensitive consumer applications
• Small Form Factor
  • 0.4mm pitch Ultra Chip Scale BGA, as small as 4mm x 4mm
  • 0.5mm pitch Chip Scale BGA, as small as 5mm x 5mm
• Easy System Integration
  • Flexible multi-volt I/O
  • 5V tolerant I/O for LVCMOS 3.3, LVTTL, and PCI interfaces
  • JTAG In-System Programmable (ISP^TM)
  • On-chip user oscillator and timer
  • Multiple temperature range support: Commercial 0 to 90°C junction (T_j), Industrial -40 to 105°C junction (T_j)
  • RoHS compliant (Pb-free) package only

• High Performance CPLD
  • f_MAX = 260MHz maximum operating frequency
  • t_PD = 4.4ns Propagation delay

• Easy to Design
  • Product term-based architecture

ispMACH 4000ZE (1.8V)

	4032ZE	4064ZE	4128ZE	4256ZE
Typical Standby Current (µA)	10	11	12	13
Density Macrocells	32	64	128	256
tPD (ns)	4.4	4.7	5.8	5.8
Fmax (MHz)	260	241	200	200
Max User I/O	32	64	96	108
Packages1	I/O + Dedicated Inputs
48 TQFP (7x7mm, 0.5mm pitch)	32+4	32+4
64 csBGA (5x5mm, 0.5mm pitch)	32+4	48+4
64 ucBGA (4x4mm, 0.4mm pitch)		48+4
100 TQFP (14x14mm, 0.5mm pitch)		64+10	64+10	64+10
132 ucBGA (6x6mm, 0.4mm pitch)			96+4
144 TQFP (20x20mm, 0.5mm pitch)			96+4	96+14
144 csBGA (7x7mm, 0.5mm pitch)		64+10	96+4	108+4

¹ Lead-free packages only

Accelerate your development time with a comprehensive set of popular Reference Designs and Development Kits optimized for the ispMACH 4000 CPLD family.

The ispMACH 4000ZE Pico Development Kit is an easy-to-use and low-cost platform for evaluating and designing with ispMACH 4000ZE CPLDs. Using the preloaded Pico Power Demo design provided with the development kit, you can measure power draw in a variety of operating modes and see common CPLD applications running on an LC4256ZE-MN144 a 256-macrocell 144-pin csBGA device. You can then build your own designs using the free downloadable reference design source code, implementing these features in less than an hour.

The ispMACH 4256ZE Breakout Board Evaluation Kit offers a convenient way for users to conduct hardware evaluations by providing easy access to densely-spaced PLD I/Os.

See CPLD Boards for more ispMACH 4000 and MachXO Evaluation Boards.

• The ispMACH 4000ZE Pico Development Kit features
  • Pre-programmed Pico Power Demo
  • ispMACH 4000ZE device (LC4256ZE-5MN144C)
  • Power Manager II device (ispPAC-POWR6AT6)
  • Battery powered
  • LCD panel
  • USB mini jack socket (Program/Power)
  • 15 x 2 expansion header for IO, I²C, and JTAG
  • Push button for global reset
  • 4-bit DIP switch
  • 3.3 and 1.8V supply rails
  • PicoView user interface
  • USB connector cable
  • QuickSTART guide
  • Marked for CE, China RoHS Environmental-Friendly Use Period (EFUP) and Waste Electrical and Electronic Equipment (WEEE) Directives

• The ispMACH 4256ZE Breakout Board Evaluation Kit features
  • Preprogrammed with hardware test program
  • ispMACH 4000ZE device (LC4256ZE-5TN144C)
  • LED Array
  • USB mini jack socket (Program/Power)
  • (4) 2 x 20 expansion header landings for IO and external power
  • 1 x 8 expansion header landing for JTAG
  • 4 x 15 hole prototyping area
  • 3.3 and 1.8V supply rails
  • USB connector cable
  • Marked for CE, China RoHS Environmental-Friendly Use Period (EFUP) and Waste Electrical and Electronic Equipment (WEEE) Directives

Lattice provides several printed circuit board (PCB) layout examples using fine-pitch (0.4 mm and 0.5 mm ball-to-ball center) ball grid array (BGA) packages to assist design and layout. In many cases alternative implementations are provided to illustrate ways to reduce fabrication cost.

• The BGA breakout and routing examples for ispMACH 4000ZE include
  • 64 csBGA
  • 64 ucBGA
  • 144 csBGA