Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Lattice Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous additional enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. Lattice Diamond software is a robust and complete software environment from entering the design to programming your Lattice device. It uses proven implementation engine technology developed for six generations of tools. Below is a list of all the major tool areas provided in the Lattice Diamond software:
The Lattice Diamond software environment provides a set of functions including the following tools.
Design projects in Lattice Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Lattice Diamond projects include the following.
Lattice Diamond includes an intuitive HDL text editor that includes keyword highlight support for: VHDL, Verilog HDL, EDIF, and the Lattice Preference Language. You also set your favorite editor as the default.
Schematic Editor view helps you visualize programmable logic designs in a graphical format using block diagrams of HDL blocks or gate-level schematics for all device families.
IPexpress view is the interface to the Lattice catalog of functional modules, reference designs, and intellectual property(IP), all optimized for Lattice programmable products. IPexpress helps accelerate the design process by helping you smoothly configure and integrate these functions into your custom design. Lattice IP cores include some of the most popular industry-standard functions such as PCI bus controllers, DDR memory controllers, Ethernet MACs, DSP functions and many more. To learn more about these IP cores, click here.
Lattice Diamond software includes dozens of DSP-function blocks optimized for use in Lattice programmable technologies. These blocks are for use in the MATLAB/Simulink DSP design environment (Available separately from The MathWorks). For more information on The MathWorks products visit their website.
Save time by analyzing your design prior to synthesis with the new integrated HDL code checking capability. Click “Generate Hierarchy” and HDL Diagram, Hierarchy, Module, and Dictionary views become available to help in analyzing your design. Additionally a number of BKM (Best Known Methods) rule checks can be run against your design. Post synthesis, the Hierarchy tab is annotated with the resource utilization to give an idea about the elements used per each level of hierarchy. It is also updated post map with physical (slices) elements.
Users of the Lattice Synthesis Engine (LSE) tool can now create and edit Synopsys Design Compiler (SDC) synthesis constraints in the new Lattice Design Constraints graphical editor. This editor automatically populates design clock, port and net names and provides real time syntax and semantic checks. It generates an SDC file that can be used with LSE.
For MachXO2 and MachXO device families the new Lattice Synthesis Engine (LSE) is available for exploring how to achieve the best results. LSE is the result of several years of development initially focused on Lattice's internal FPGA architecture development. LSE supports both Verilog and VHDL languages and uses SDC format for constraints. It is integrated into the Lattice Diamond design software as a synthesis tool choice when a supported device family is selected.
Lattice Diamond includes the industry-leading synthesis solution, Synopsys Synplify Pro for Lattice, with a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Synplify Pro for Lattice also includes HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Other advanced features include the following.
Design Planner in ispLEVER incorporated several functions in a separate tool. These functions are now individual views in Lattice Diamond and work seamlessly with the other views. A key component is the Spreadsheet View. This view allows the ability to enter and view design constraints such as pin assignments, clock resource usage, global preferences, timing preferences and more. Spreadsheet View provides cross probing to several other views and works with the File List view for managing multiple constraints files. When migrating to a lower cost device in one of the device families, Spreadsheet View can show the incompatible pins.
Package View allows easy graphical assignment of signals to pins. Package View also provides a graphical representation of SSO noise analysis to check noise caused by parallel output switching. Package View provides cross probing to several other views including Spreadsheet View, Floorplan View and others. When migrating to a lower cost device in one of the device families, Package View can show the incompatible pins.
Lattice Diamond provides several abstractions for design and device tasks. Floorplan View provides the ability to view and edit placement constraints. Physical View provides a detailed read-only view of the physical routing of paths for more detailed understanding of timing issues. Netlist View provides browsing of design ports, instances, and nets for drag and dropping into other views such as Package View for setting constraints. NCD View provides access to detailed usage information of physical components such as SLICEs, PIOs, IOLOGIC, and other elements. Device View provides the ability to browse device specific resources and cross-probe to other views. Together these views provide access to the information needed to analyze and constrain the design’s implementation.
ECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization without having to use a full editor such as EPIC.
EPIC device editor provides detailed access and editing of the physical implementation of your design. Physical details like route interconnect, physical element programming, and I/O buffer configuration can be examined or directly edited after the PAR process, giving you ultimate control.
The new Timing Analysis View offers an easy to use graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path schematic views instantly. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis View is rapidly updated analysis when timing constraints are changed, including clock jitter analysis. No longer must you re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is directly run.
Power Calculator uses highly accurate data models along with a data driven power model to provide power estimation and calculation results, graphical power displays, and reports. Thermal resistance options can be used to model real world thermal conditions including heatsinks, airflow, and board complexity. The data driven approach of Power Calculator provides very accurate results for both power estimation and calculation giving you high confidence when targeting the specific power budgets of low power design applications.
Reveal Inserter uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. Reveal features the ability to use, multi-event triggering which can be dynamically changed at run-time.
Reveal Analyzer features the ability to use, multi-event triggering which can be dynamically changed at run-time and an integrated waveform for displaying captured events from the target FPGA. New in Lattice Diamond is a more streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display. And, downloading trace data or setting complex trigger configuration is really fast.
Lattice Diamond software adds capabilities for scripting the design flow. In addition to the Tcl console tab in the environment, a separate Tcl console application allows running scripts independently. Lattice Diamond specific Tcl command dictionaries are available for the following areas.
Lattice Diamond provides easy export of designs to simulators through the Simulation Wizard, including support for multi-file testbenches. The Simulation Wizard will guide you through all the necessary steps to get your design to a simulator in the format you want it. Simulation Wizard is the easy way to get exactly what you want.
Lattice Diamond includes the comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. When using Lattice Diamond with the free license, simulation is enabled for Active-HDL Web Edition II which offers many of the same features with less capacity. Aldec Active-HDL Lattice Edition II and Active-HDL Web Edition II are available on Windows platforms only.
Fully integrated into Diamond and standalone, Programmer allows easy direct normal programming of single or multiple FPGA devices. For more advanced programming features, ispVM is still available.
Diamond Deployment Tool provides an intuitive wizard approach to create the appropriate device programming file in the format required by your deployment method. Getting the job done more quickly is the goal of these tools.
ispVM System is provided with Lattice Diamond, and is also available as a stand-alone device programming manager. The ispVM System™ is a comprehensive design download package that provides an efficient method of programming Lattice devices using JEDEC and Bitstream files generated by ispLEVER, PAC-Designer, and other design tools. For more detailed information on ispVM, visit the ispVM System page.
© Lattice Semiconductor Corporation 2012
