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Diamond SoftwareLattice Diamond is the new flagship logic design environment for Lattice FPGA products. Diamond is available as a download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either a free license or a subscription license. Diamond software only needs to be downloaded and installed once. Diamond Software Free LicenseA free license can be requested from the Lattice website. This license provides access to many popular Lattice devices such as MachXO and LatticeECP2 at no cost. It also includes Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Web Edition II simulation software. Diamond Software Subscription LicenseA subscription license can be purchased which adds support for all Lattice FPGAs including the latest LatticeECP3 devices. It includes Synopsys Synplify Pro for Lattice synthesis and Aldec Lattice Edition II mixed language simulator for increased capacity and performance. The subscription license also enables both the new Diamond software and existing ispLEVER software from a single license.
Powerful New FeaturesDesign Exploration Made EasyProjects / Implementations / StrategiesDesign projects in Diamond offer an order of magnitude increased functionality by allowing more robust projects and capabilities that allow design exploration. Key improvements to Diamond projects include the following:
Analyzing Your Design with HDL Code CheckingSave time by analyzing your design prior to synthesis with the new integrated HDL code checking capability. Ease of Use ThroughoutUser Interface for a New Generation of ToolsThe Diamond user interface combines leading edge features and customization while offering better ease of use. All the tools in Diamond now open in “Views” integrated into a common Diamond user interface and have the ability to be detached in separate windows. Once the operation for a single tool view is learned, this knowledge can be applied to other views. New features like the Start Page and Reports view allow easy access to information. Speeding Common FunctionsECO Editor provides quick access to commonly used netlist editing functions such as sysIO settings, PLL parameters, and memory initialization. Programmer allows fast reprogramming of FPGAs once the hardware configuration has been setup with ispVM. Getting the job done more quickly is the goal of these tools More Efficient Design FlowTiming Analysis Easier and FasterThe new Timing Analysis view offers an easy to use graphical environment for navigating timing information. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. No longer must you re-implement your design to re-run a TRACE report. Easy Design Export to SimulatorsDiamond provides easy export of designs to simulators through the new Simulation Wizard. Scripting with TCLDiamond software adds new capabilities for scripting the design flow. Diamond specific TCL command dictionaries are available for projects, netlists, HDL code checking, power calculation, and hardware debug insertion and analysis.
Complete Design EnvironmentDiamond software is a robust and complete software environment from entering the design to programming your Lattice device. It uses proven implementation engine technology developed for six generations of tools. Diamond includes a complete set of tools covering all aspects of FPGA design.
Powerful Third-Party ToolsSynopsys Synplify® Pro for Lattice SynthesisLattice Diamond includes the industry-leading synthesis solution, Synopsys Synplify Pro for Lattice, with a range of tools and features that help you manage large designs, and extract the very best fit and performance, optimized for Lattice FPGAs. Synplify Pro for Lattice also includes HDL Analyst, which automatically produces an RTL schematic of your design for analysis and cross-probing with RTL source code. Other advanced features include mixed VHDL and Verilog synthesis support, compile points, automatic re-timing (balancing registers across combinatorial logic) for improved performance, and automatic gated-clock and generated clock conversion for efficient implementation of RTL written for an ASIC into an FPGA. Aldec Active-HDL® SimulationThe Lattice Diamond subscription license includes the fast, comprehensive and feature-rich simulation environment Active-HDL Lattice Edition II from Aldec. Active-HDL Lattice Edition II features mixed language simulation of VHDL and Verilog, and many advanced verification and debug features such as Language Assistant, Code Execution Tracing, Advanced Breakpoint Management and Memory Viewing. The Lattice Diamond free license includes Active-HDL Web Edition II which offers many of the same features with less capacity. Aldec Active-HDL Lattice Edition II and Active-HDL Web Edition II are available on Windows platforms only.
Learn More About Diamond
Choosing The Right Software ToolThe following matrix summarizes some of the more important features of the current Lattice FPGA & logic design software tools. For current Lattice FPGA devices, Lattice Diamond is the recommended design software. For Lattice CPLD devices, ispLEVER Classic is the required design software.
Note: Lattice Diamond subscription license allows either Diamond or the previous ispLEVER software to be run. Aldec simulation for Windows floating license requires a USB ID Key (ALDEC-USBKEY). Both of these products are available via the Lattice on-line store. |
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Lattice Diamond design software offers leading-edge design and implementation tools optimized for cost sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER featuring design exploration, ease of use, improved design flow, and numerous other enhancements. The combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before.
