Generic Digital Crosspoint (GDX) devices represent a class of high-density programmable component, distinct from complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The diagram below shows the evolution of these devices. Each successive family built on the previous concepts: starting from initial GDX family to latest high speed Switching and interfacing ispGDX2 family. Digital Crosspoint devices are available to support 5.0V, 3.3V, 2.5V and 1.8V designs and have been optimized for fast, cost-effective integration of complex interface logic and signal routing applications.
The ispGDX2 family consists of devices with up to 16 high speed (800 MHz) SERDES, up to four 360MHz sysCLOCK PLLs, sysIO interface capability and is available in 64, 128 and 256 I/Os. With blazing fast 3.0ns input-to-output speeds and versatile sysIO buffers, the ispGDX2 family supports the most demanding interfacing and interconnect needs of next-generation system designs.
The ispGDXV (3.3V) family consists of devices with 80, 160 and 240 I/Os. The original 5V ispGDX Family is available in 80, 120 and 160 I/O versions.
| Family | Registers | Fastest Speed | sysCLOCK PLL | sysIO Interfaces | sysHSI Block | I/Os | |
|---|---|---|---|---|---|---|---|
| tPD (ns) | Fmax (MHz) | ||||||
| ispGDX2V | 64-256 | 3.0 | 360 | Yes | Yes | Yes | 64-256 |
| ispGDXV | 80-240 | 3 | 250 | No | No | No | 80-240 |
Click here for information on related older device families
© Lattice Semiconductor Corporation 2012
