Each LatticeECP3 device can quickly be configured using one of several flexible options:
Dual-boot images are supported for applications requiring reliable remote updates of configuration data for the LatticeECP3 FPGA. After the system is running with a basic configuration, a new boot image can be downloaded remotely and stored in a separate location in the configuration storage device. Any time after the update the LatticeECP3 can be re-booted from this new configuration file. If there is a problem, such as corrupt data during download or incorrect version number with this new boot image, the LatticeECP3 device can revert back to the original backup golden configuration and try again. This all can be done without power cycling the system.
The LatticeECP3 devices contain non-volatile memory elements that can be used for the storage of a 128-bit customer specific decryption key. Bitstream files can be encrypted with this key prior to programming into the configuration memory. As the encrypted bitstream enters the FPGA it is decrypted using the key stored on the device. This capability provides a method to combat design piracy and overbuilding.
LatticeECP3 devices have dedicated logic to perform Cycle Redundancy Code (CRC) checks. During configuration, the configuration data bitstream can be checked with the CRC logic block. In addition, the LatticeECP3 device can also be programmed to utilize a Soft Error Detect (SED) mode that checks for soft errors in configuration SRAM.
LatticeECP3 devices feature TransFR I/O that allows I/O states to be frozen during device configuration. This allows the devices to be updated in the field with a minimum of system disruption and downtime, allowing designers to meet the dual requirements of high system uptime, such as "5 nines" (99.999%) availability, and field updating of logic. The following diagrams show the four steps of achieving these updates using the TransFR I/O feature of the LatticeECP3.
© Lattice Semiconductor Corporation 2012
