The LatticeECP3™ FPGA family includes many features for video applications. For example, DisplayPort, SMPTE standards (SD-SDI, HD-SDI and 3G-SDI) and DVB-ASI can be implemented with 16 channels of embedded SERDES/ PCS. 7:1 LVDS video interfaces like ChannelLink and CameraLink can be supported by the generic DDRX2 mode on the I/O pins. When configuring to TRLVDS mode, the I/O pins on banks 0 and 1 can also be used to receive the TMDS signals of DVI or HDMI video standard.
Board Features
- Video interfaces for interconnection to video standard equipment
- Allow the demonstration of SD/HD/3G-SDI, DisplayPort and PCI Express (x4) interfaces using SERDES channels
- High speed Mezzanine connector connected to SERDES channels for future expansion
- Allows the demonstration of LVDS video standards – ChannelLink and CameraLink
- Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
- Allows the demonstration of receiving TMDS signals using the DVI interface
- On-board Boot Flash with Serial SPI Flash memory device
- Shows interoperation with high performance DDR2 memory components
- Driver-based “run-time” device configuration capability via an ORCAstra or RS232 interface
- SMAs for external high-speed clock / PLL inputs
- Switches, LEDs and LCD display header for demo purposes
- Mictor connector for using Logic Analyzer in the debugging phase
- Input connection for lab-power supply
- Power connections and power sources
- ispVM™ programming support
- On-board and external reference clock sources
- Various high-speed layout structures
- User-defined input and output points
- Performance monitoring via test headers, LEDs and switches
PCB Revision Notes
Starting in March 2010, Lattice will be shipping Revision C LatticeECP3 Video Protocol boards. This revision includes some minor changes which are summarized below, and detailed in the Revision C User's Guide.
- Pull-up resistors added to the DVI Rx and DDR2 DQS signals
- Provision for resistor between the P and N reference clocks of SERDES Quad C
- Gennum clock generators (GS4911) on U2 and U3 are not populated, as this feature is not used in any of the standard evaluation modes.
Demos
Ordering Information
For other ordering options contact your local Lattice sales representative.
© Lattice Semiconductor Corporation 2012
