LatticeECP3 PCI Express Root Complex Lite x1 Demo

PCI Express is a point-to-point serial protocol that allows connectivity in board to chip-to-chip, board-to-board, and box-to-box applications. In a PCI Express fabric, a link is established between a downstream port and upstream port of in a PCI Express hierarchy  Applications connecting to the upstream port of a switch or an endpoint can use the Lattice PCI Express Root Complex (RC) Lite IP core for the required downstream port.  The PCI Express RC Lite Demo demonstrates a PCI Express link between two Lattice EPC3 devices.

Overview

The Lattice PCI Express RC Lite x1 native demo uses two LatticeECP3 IO Protocol boards connected via SMA cables to illustrate a x1 PCI Express link between two ports.

• One board functions as the downstream port (root complex) and is implemented in a design including the PCI Express RC Lite IP x1 native core, user interface termination logic, and LED logic. 
• The other IOP board functions as the upstream port (endpoint) and is loaded with an endpoint design including the PCI Express Endpoint IP x1 native core, user interface termination logic, and LED logic.

After the FPGA device is programmed, each board goes through the following sequence.

1. Performs Receiver Detection of the link partner
2. Performs Receiver Clock Data Recovery
3. Starts training the link
4. Exchanges Initial Credits
5. Enters L0 readying for TLP exchange

Once in L0 state,

1. The Endpoint detects state of dipswitch SW4-8 to send interrupt message to the Root Complex
2. The Root Complex decodes interrupt message to light up the appropriate LED.

Downloads

Demo User Guide
Demo Files

Related Pages

• PCI Express RC Lite IP Core
• PCI Express Endpoint IP Core
• LatticeECP3 IO Protocol Board
• PCI Express Solutions