The LatticeECP3 SERDES Eye/Backplane demo demonstrates the performance of the LatticeECP3 SERDES I/O at 3.125 Gbps. The basic concept of the design is a quad-based PRBS Generator/checker that transmits four channels of parallel data to a PCS quad. In turn, the PCS SERDES channels serialize the data in the transmit direction, and de-serialize it in the receive direction. The serial data stream can be:
In both cases, a backplane of variable length can be included in the serial path.
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© Lattice Semiconductor Corporation 2012
