Power is an important consideration in today’s marketplace. Lower power operation helps designers meet the thermal and reliability requirements while reducing the overall system cost and design complexity.
The LatticeECP3 is the third generation of the value-based LatticeECP FPGA series. It extends the functionality of prior generation families to new levels and provides designers with enhanced features and capabilities at a fraction of the power consumption and cost of competing devices. The power advantage is achieved by using various process and architectural enhancements as well as software power optimization techniques.
- Low-power 65nm process with 4-input look-up table (LUT) fabric
- Upto 80% lower static power, and 50% lower total power relative to the competition
- Less than 110mW power per channel at 3.2Gbps
Static (Quiescent ) Power Consumption of LatticeECP3 vs. Competing FPGAs
Figure 1#: Quiescent Power Consumption of LatticeECP3 vs. Competing FPGAs
The LatticeECP3 is 72% to 85% Lower Quiescent Power than the competition at ~100K LUTs (15%-28% of the Static Power of the competition).
Total Power Consumption of LatticeECP3 vs. Competing FPGAs
Figure 2#: Total Power Consumption of LatticeECP3 vs. Competing FPGAs
The LatticeECP3 is 45% to 75% Lower Total Power than the competition at ~100K LUTs (25% to 55% of the total power of the competition).
#For additional information on the methodology and measurements please refer to:
Power Estimation and Analysis Tools
Lattice provides the ispLEVER Power Calculator in your FPGA design tools to help you model power consumption in a variety of operating environments. The power calculator is an environment-aware power model based on device and package selection, operating conditions and resource utilization.
© Lattice Semiconductor Corporation 2012
