3G SERDES Built For Real-World Applications

The LatticeECP3™ FPGA family combines a high-performance FPGA fabric, high-performance I/Os and up to 16 channels of embedded SERDES with associated Physical Coding Sublayer (PCS) logic.  Each channel of PCS logic contains dedicated transmit and receive circuitry for high-speed, full-duplex serial data transfer of up to 3.2 Gbps.  The PCS logic in each channel can be configured to support an array of popular data protocols including GbE, XAUI, PCI Express PIPE, SRIO, CPRI, OBSAI, SD-SDI and HD-SDI. In addition, the protocol-based logic can be fully or partially bypassed in a number of configurations to allow users flexibility in designing their own high-speed data interface. Each SERDES channel consumes less than 110mW of power at 3.2Gbps enabling the implementation of high speed Serial Protocols at the Lowest Power. White Paper - High-Speed SERDES Interfaces In High Value FPGAs

LatticeECP3 SERDES Features and Benefits

• Up to 16 Channels of High-Speed SERDES
• 150 Mbps to 3.125 Gbps per channel
• Low Power: 110mW Per Channel @ 3.2 Gbps
• IEEE802.3-2002 XAUI Jitter Compliant
  
  • High Rx Jitter Tolerance Exceeds 0.7UI Worst Case @ 3.2 Gbps
  • Low Tx Jitter Less Than 0.35UI Worst Case @ 3.2 Gbps
• Built-In Pre-Emphasis and Equalization for Superior BER
• Quad based architecture with mix and match of different protocols within a quad
• Full Function Embedded Physical Coding Sub-layer (PCS) Logic Supporting Industry Standard Protocols
  
  • Up to 16 channels of full-duplex data supported per device
  • Multiple protocol support on one chip
  • Supports popular 8b10b-based packet protocols
  • SERDES Only mode allows direct 8-bit or 10-bit interface to FPGA logic

High-Value, Low-Power Serial Protocol Solutions

CPRI Low Latency Option

The Physical Coding Sub-layer (PCS) offers a low latency option which enables a smaller, cleaner CPRI implementation.

Enhanced SMPTE Support

In a broadcast studio, or a satellite head-end or cable head-end, the designers do not necessarily have prior knowledge of what the Rx data rate will be.  As a result they would like to see support for various popular data rates such as SD-SDI (SMPTE259M) at 270Mbps and HD-SDI (SMPTE292M) at 1.4835Gbps.

The LatticeECP3 SERDES is architected for channel independence enabling any rate, any channel, any direction for SD, HD and 3G.  This is done with a new x11 divider setting and added independent Rx clocking per channel.

Demos