The LatticeSC/M (System Chip/MACO) family of FPGAs combines a high-performance FPGA fabric, 3.8Gbps SERDES and PCS, 2Gbps Parallel I/Os, low-power 1V Vcc option, large embedded RAM, and embedded ASIC blocks to provide the highest performing FPGA in the industry.
Designed with the needs of today's high-speed connectivity-based systems in mind, LatticeSC family delivers best in class solutions for high throughput standards like Ethernet, PCI Express, SPI4.2 and high speed Memory Controllers. LatticeSC is equipped with embedded memory, hierarchical clocking and clock management resources for high-end system designs. For low-cost, system-level integration, the LatticeSCM family offers MACO (Masked Array for Cost Optimization): up to 12 embedded structured ASIC blocks per device with a variety of pre-engineered IP blocks.
Key Features
- High Performance FPGA Fabric
- 15K to 115K Four Input Look-up Tables (LUT4s)
- 139 to 942 I/Os
- 700MHz global clock; 1GHz edge clocks
- Design for Low Power: 1V Vcc Option Reduces Fabric Power Consumption By 44%
- High Speed SERDES: 4 to 32 SERDES per device @ 600Mbps to 3.8Gbps featuring:
- Pre-emphasis and equalization
- Low power (105mW per channel)
- Embedded Physical Coding Sublayer (PCS) supports: PCI Express GbE, XAUI, SONET, 1G Fibre Channel, 2G Fibre Channel and Serial Rapid IO
- PURESPEED Technology: 2Gbps Parallel I/O
- Input Delay (INDEL) with Adaptive Input Logic (AIL) dynamically aligns data on a per-pin basis for robust high performance source synchronous I/O support
- Supports generic DDR up to 2Gbps; generic SDR up to 1Gbps; Single-ended memory interfaces up to 800Mbps
- Comprehensive standards support: LVCMOS; LVTTL; PCI, PCI-X; LVDS, Bus-LVDS, MLVDS, LVPECL; with programmable On Device Termination (ODT) options
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Development Kits, Evaluation Boards
Development Kits:
- LatticeSCM PCI Express Development Kit: LatticeSCM PCI Express Development Kits are solutions that enable designers to evaluate Lattice's PCI Express IP capabilities in a complete hardware/software development environment, modify and test different functionality, and then create new designs using a known good starting point. The kits include several components to help accelerate quick prototype development, including a demo package with evaluation bitstreams, drivers, and GUI, RTL source for top-level project directories, documentation, and evaluation boards.
Evaluation Boards: Lattice has developed the following platforms for evaluating the features and performance of the LatticeSC/M FPGA.
- LatticeSC Communications Board: This board is an advanced communications platform that will help you explore how the LatticeSC performs to a variety of communications standards and specifications. Features of this board include a 300-pin MSA transponder interconnection to evaluation Single Data Rate (SDR) performance for SFI-4.1/XSBI applications, a Molex VHDM interconnection to system packet interface level 4-phase 2 (SPI-4.2), a 200-pin SODIMM socket supporting 64-bit 200-pin DDR-2 SDRAM, numerous SMA test points for high-speed SERDES and Clock I/O, and much more.
- LatticeSC PCI Express x4 Evaluation Board: This board will help you evaluate the performance of the LatticeSC in additional application spaces. Key features of this board include a x4 PCIexpress edge connector / form-factor, on-board DDR2 Memory, BNC edge connectors for Digital Video Interface, SMA connectors for SERDES I/O, LVDS evaluation, and external clock I/O, and more.
- LatticeSC PCI Express x1 Evaluation Board: Key features of this board include a x1 PCIexpress edge connector / form-factor, On-board QDR2 and RLDRAM2 Memory, SATA Host/Target, 1Gbe SFP, SMA connectors for SERDES I/O, LVDS evaluation, and external clock I/O, Tri-speed Ethernet PHY with RJ45 jack, RS-232 port, and more.
- LatticeSC SFI-5 Evaluation Board: Key features of this board include a 40-Gigabit SFI-5 interface via a 300-pin MSA transponder interconnection, SERDES high-speed interface SMA test points and clock connections, SERDES connections to RJ-45 connection for physical layer testing to CAT5 cable standards, 36-bit QDR2+ memory device as well as on-board power circuitry and switches/LEDs for user I/O. This board is primarily designed for use with the Lattice SFI-5 IP core and interoperation with 40G transponders via the provided 300-pin MSA.
Device Selection Guide
LatticeSC and LatticeSCM FPGA Family
| Parameter |
LFSC15 |
LFSC25 |
LFSC40 |
LFSC80 |
LFSC115 |
| Logic Resources – LUTs (K) |
15.2 |
25.4 |
40.4 |
80.1 |
115.2 |
| sysMEM EBR RAM Blocks (18Kb / Block) |
56 |
104 |
216 |
308 |
424 |
| Embedded Memory (Mbits) |
1.03 |
1.92 |
3.98 |
5.68 |
7.80 |
| Max. Distributed Memory (Mbits) |
0.24 |
0.41 |
0.65 |
1.28 |
1.84 |
| Max. # of SERDES Channels (3.8Gbps) |
8 |
16 |
16 |
32 |
32 |
| DLLs |
12 |
12 |
12 |
12 |
12 |
| PLLs |
8 |
8 |
8 |
8 |
8 |
| MACO Blocks (LatticeSCM only) |
4 |
6 |
10 |
10 |
12 |
| Packages |
I/O / SERDES Count |
| 256-ball fpBGA (17 x 17 mm) |
139 / 4  |
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| 900-ball fpBGA (31 x 31 mm) |
300 / 8 |
378 / 8 |
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| 1020-ball fcBGA (33 x 33 mm) |
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476 / 16 |
562 / 16 |
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| 1152-ball fcBGA (35 x 35 mm) |
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604 / 16 |
660 / 16 |
660 / 16 |
| 1704-ball fcBGA (42.5 x 42.5 mm) |
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904 / 32 |
942 / 32 |
© Lattice Semiconductor Corporation 2012
