The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device programming and configuration. The Figure below provides an overview of the arrangement of Flash and SRAM configuration cells within the device.
At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration cells that control the operation of the device. This is done with massively parallel buses enabling the parts to operate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.
The on-chip Flash enables a single-chip solution eliminating the need for external boot memory and thereby reducing the solution footprint. The single die allows smaller packages to be used than currently have been delivered using hybrid stacked die approaches.
~3K LUT Hybrid Non-volatile Device and 5K LUT True Non-volatile Device
The FlashBAK capability of the parts enables the contents of the EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the device configuration.
Serial memory is available to allow the storage of small amounts of data such as calibration coefficients and error codes.
| Device | TAG Memory (Bits) |
|---|---|
| XP2-5 | 632 |
| XP2-8 | 768 |
| XP2-17 | 2186 |
| XP2-30 | 2640 |
| XP2-40 | 3384 |
For applications where security is important, the lack of an external bit stream provides a solution that is inherently more secure than SRAM only FPGAs. Three features further enhance the inherent security of this solution:
© Lattice Semiconductor Corporation 2012
