FPSCs from Lattice: ORT82G5/42G5

Lattice Semiconductor has developed the industry's fastest device for high-speed serial backplane data transmission. The ORCA ORT82G5 is made up of backplane transceivers containing eight channels, each operating over a range from 600 Mbits/s to 3.7 Gbits/s, with a full duplex synchronous interface with built-in Clock and Data Recovery (CDR), along with more than 400K FPGA functional gates.

The ORT42G5 is made up of backplane transceivers containing four channels, each operating over a range from 600 Mbits/s to 3.7 Gbits/s, along with more than 400K FPGA functional gates.

Both the ORT42G5 and ORT82G5 FPSCs offer a clockless high-speed interface for interdevice communication on a board or across a backplane. The built- in clock recovery of the ORT82G5/ORT42G5 allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane.

ORT42G5/ORT82G5 Products

Device	ORT82G5	ORT42G5
FPGA Usable Gates	333-643K	333-643K
PFUs	1,296	1,296
LUTs	10,368	10,368
Registers	12,780	12,780
PFU RAM Bits	277K	277K
EBR RAM Bits	111K	111K
FPGA User I/O	372	204
Package	680PBGAM	484PBGAM
I/O Compatibility	1.5/1.8/2.5/3.3V	1.5/1.8/2.5/3.3V
SERDES Channels	8	4
Data Rate per Channel	3.7Gbps	3.7 Gbps

 

Features

• High-speed SERDES with programmable serial data rates from 0.6 Gbits/s to 3.7 Gbits/s.
• Asynchronous operation per receive channel (separate PLL per channel)
• Provides a 10 Gbits/s backplane interface to switch fabric with protection

Some of the Intellectual Property Features include:

• Programmable logic provides a variety of yet-to-be standarized interface functions
• POS-PHY interface for 10 gbits/s SONET/SDH and OTN systems and some 10 Gbits/s Ethernet systems
• Ethernet MAC functions at 10/100 Mbits/s, 1 Gbits/s and 10 Gbits/s

• Provides the FC-0 and FC-1 layers of the FibreChannel FC-PH Specification in the Embedded ASIC Core, including:
  • 8b/10b encoders/decoders
  • Link Synchronization State Machine (to ANSI X3.230-1994, Clause 12)
• User has the ability to perform 1G or 2G FibreChannel on a single device, allowing a seamless upgrade path
• Ideal for Chip-to-Chip communications
• Bit Error Rate of less than 10^-12 across 6 inches of FR-4 backplane and 24 inches of coax cable.

Lattice Advantages:

• Lowest power of any programmable SERDES vendor - 225mW @ 3.125Gbps, per channel including pre-emphasis and 8b/10b endecs.

Lattice IP Cores and Reference Designs

FPSC design is supported by a variety of pre-tested, reusable functions optimized for the ORT82G5/42G5 architecture. Browse the See Also section of this page for ispLeverCORE Connection Partner links.

Lattice IP Cores

• Convolutional Encoder
• CSIX Level 1
• CSIX to PI40
• DDR SDRAM Controller - Non-Pipelined
• Ethernet MAC Cores
• Multi-channel DMA Controller
• Reed-Solomon Decoder
• Reed-Solomon Encoder
• Serial RapidIO - Physical Layer Interface
• Turbo Decoder
• Turbo Encoder

Lattice Reference Designs

• 8b/10b Encoder/Decoder
• DDR SDRAM Controller
• QDR Memory Controller

ORT82G5 Evaluation Boards

The ORT82G5 High-Speed SERDES Briefcase Board includes a number of features to help the user thoroughly evaluate the performance of the ORT82G5 device, or aid in the development of custom designs. The board features numerous I/O connections, SMA connectors for high-speed signaling, on-board clocks (external clocks can be provided), on-board power management, and more.

View the ORT82G5 High-Speed SERDES Briefcase Board webpage.

ORT42G5 Evaluation Boards

The Lattice ORT42G5 Evaluation Board provides an evaluation and development platform for the Lattice ORT42G5 device. This versatile board contains all the features you need to evaluate the ORT42G5 device, or aid in your development process.

View the ORT42G5 Evaluation Board webpage.