The ORT8850 devices offer a clockless, high-speed interface for interdevice communication on a board or across a backplane. The built-in clock recovery of the ORT8850 FPSCs allows for higher system performance, easier-to-design clock domains in a multiboard system, and fewer signals on the backplane.
The ORT8850 is available in medium- and high-density versions. While both feature 8 x 850Mbits/s high-speed interfaces, the ORT8850L offers up to 397K FPGA Functional gates and 278 user I/Os. The ORT8850H offers up to 899K FPGA Functional gates and 297 user I/Os.
Features
Embedded Core Features (Serial):
- Implemented in an ORCA Series 4 FPGA array
- Allows a wide range of high-speed backplane applications including SONET transport.
- No knowledge of SONET/SDH needed in generic applications. Simply supply data, 78 MHzý106 MHz clock, and a frame pulse.
- High-Speed Interface (HSI) function for clock/data recovery serial backplane data transfer without external clocks.
- Eight-channel HSI function provides 850 Mbits/s serial interface per channel for a total chip bandwidth of 6.8 Gbits/s (full duplex).
- HSI function uses the proven Lattice Semiconductor 850 Mbits/s serial interface core. Rates from 212 Mbits/s to 850 Mbits/s are supported directly (Lower rates directly supported through decimation and interpolation).
- LVDS I/Os compliant with EIA*-644, support hot insertion. All embedded LVDS I/Os include both input and output on-board termination to allow long-haul driving of backplanes.
- Low-power HSI core
- Low-power LVDS buffers
- Programmable STS-1, STS-3, and STS-12 framing
- Independent STS-1, STS-3, and STS-12 data streams per quad channels
- 8:1 data multiplexing/demultiplexing for 106.25 MHz byte-wide data processing in FPGA logic
- On-chip, Phase-Lock Loop (PLL) clock meets B jitter tolerance specification of ITU-T recommendation G.958.
- Powerdown option of HSI receiver on a per-channel basis
- Pseudo-SONET scrambler/descrambler
- HSI automatically recovers from loss-of-clock once its reference clock returns to normal operating state.
- Frame alignment across multiple ORT8850 devices for work/protect switching at OC-192/STM-64 and above rates
- In-band management and configuration through transport overhead extraction/insertion
- Supports transparent mode where the only insertion is A1/A2 framing bytes
- Streamlined pointer processor (pointer mover) for 8 kHz frame alignment to system clocks
- Built-in boundry scan ( IEEE 1149.1 JTAG)
- FIFOs align incoming data across all eight channels, two groups of four channels or four groups of two channels. Optional ability to bypass alignment FIFOs.
- 1 + 1 protection supports STS-12/STS-48 redundancy by either software or hardware control for protection switching applications. STS-192 and above rates are supported through multiple devices.
- ORCA FPGA soft intellectual property core support for a variety of applications
- Programmable STM pointer mover bypass mode
- Programmable STM framer bypass mode
- Programmable inverted data framing per channel
- Programmable CDR bypass mode (clocked LVDS high-speed interface)
- Redundant outputs and multiplexed redundant inputs for CDR I/Os allow for implementation of eight channels with redundancy on a single device.
Lattice IP Cores and Reference Designs
FPSC design is supported by a variety of pre-tested, reusable functions optimized for the ORT8850 architecture. Browse the See Also section of this page for ispLeverCORE Connection Partner links.
Lattice IP Cores
Lattice Reference Designs
ORT8850 Evaluation Boards
The ORT8850 FPSC Evaluation Board is a complete hardware kit that allows the user to evaluate the performance and characteristics of the ORT8850 device and aid in the development process.
View the ORT8850 Evaluation Board webpage.
© Lattice Semiconductor Corporation 2012
