LPDDR SDRAM Controller

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User Manuals

Overview

The LPDDR Synchronous Dynamic Random Access Memory (SDRAM) Controller is a general-purpose memory controller that interfaces with industry standard LPDDR memory devices/modules compliant with JESD209B, LPDDR SDRAM Standard, and provides a generic command interface to user applications. This IP core reduces the effort required to integrate the LPDDR memory controller with the remainder of the application and minimizes the need to directly deal with the LPDDR memory interface.

Features

Interfaces to industry standard LPDDR SDRAM according to JESD209B
Double-data rate architecture; two data transfers per clock cycle
Bi-directional data strobe per byte of data (DQS)
Programmable auto refresh support
Data mask support – one mask per byte
Power down and deep power down support
Supports power-on initialization
Supports re-initialization after a deep power down
Dynamic I/O training after initialization
Periodic I/O retraining after an auto refresh burst
Dynamic memory clock power off during self refresh, power down and deep power down operations
Supports single-port operation
Supports full, half and quarter array self refresh
Status register read support
TCSR programmability through MRS

The LPDDR SDRAM Controller is available as an IPexpress user configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Performance and Resource Utilization

MachXO2¹
IP Core	Parameter Settings²	SLICEs	LUTs	Registers	I/O	PAR Start Point	f_MAX (MHz)
LPDDR SDRAM Controller Configuration 1	User Guide Table 3-1 parameter defaults	814	1530	911	149	1	136.4
LPDDR SDRAM Controller Configuration 2		705	1314	804	149	1	136.6
LPDDR SDRAM Controller Configuration 3		729	1409	969	143	1	142.9
LPDDR SDRAM Controller Configuration 4		729	1409	969	143	1	142.9

1. Performance and utilization data are generated using a LCMXO2-7000HE-6BG256C device in Lattice Diamond 1.3 design software. Performance may vary when using this IP core in a different density, speed or grade within the MachXO2 family.
2. SDRAM data path width of 16 bits.

Ordering Information

Family

Part Number

MachXO2

LPDDRCT-WB-M2-U

IP Version: 1.0
Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.