LatticeMico32 Open, Free 32-Bit Soft Processor

The LatticeMico32™  is a 32-bit Harvard, RISC architecture "soft" microprocessor, available for free with an open IP core licensing agreement.  The LatticeMico32 provides the visibility, flexibility and portability that you expect in an open source hardware design. Everything you need is provided, including software development tools  (via LatticeMico™ System) and evaluation boards to try out your designs in hardware.

 

By combining a 32-bit wide instruction set with 32 general purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Using a RISC architecture, the core consumes minimal device resources, while maintaining the performance required for a broad application set.  To accelerate the development of microprocessor systems, several optional WISHBONE compatible peripheral components may be integrated with the LatticeMico32.

 

 Features

• Optimized for Lattice FPGA Devices
• Performance Enhanced Feature Set
  • RISC architecture
  • 32-bit data path and 32-bit instructions
  • 32 general purpose registers
  • Handles up to 32 external interrupts
  • Optional instruction and data caches
  • Dual WISHBONE memory interfaces (Instruction and Data)

 

WISHBONE Compatible Peripheral Components

To accelerate the development of microprocessor systems, several optional WISHBONE compatible peripheral components may be integrated with the LatticeMico32.

• Memory controllers
  • DDR, DDR2 & DDR3 SDRAM
  • Asynchronous SRAM
  • On-chip Block Memory
  • SDRAM controller
  • On-chip dual port memory
  • SPI Flash
  • Parallel Flash
• I/O 
  • 32-bit Timer 
  • DMA Controller 
  • GPIO 
  • I2C Master Controller 
  • SPI
  • Tri-Speed Ethernet MAC
  • UART
  • PCI Target

Three Configurations to Optimize Area and Performance

• Basic 
  • No Multiplier
  • Multicycle Shifter
  • No Cache
• Standard
  • Multiplier
  • Pipelined Shifter
  • 8K I-Cache, No D-Cache
• Full
  • Multiplier
  • Pipelined Shifter
  • 8K I-Cache, 8K D-Cache

Performance and Resource Utilization¹

Lattice FPGA Family	Configuration	LUTs	fMAX (MHz)
LatticeECP3	Standard	2,370	115
LatticeXP2TM	Standard	2,406	85
LatticeECP2/M	Standard	2,497	110

¹Performance and utilization characteristics are generated using Lattice Diamond software. When using the LatticeMico32 in a different density, speed, or grade within the Lattice FPGA family, performance may vary.

For information about the LatticeMico32 for other Lattice FPGA families, please contact your local Lattice Sales Office.

Looking for an 8-bit microcontroller?  Check out the LatticeMico8.

 

Development Tools

LatticeMico System is to be used to implement a LatticeMico32 system with attached peripheral components. It is based on the Eclipse C/C++ Development Tools Environment, which is an industry open-source development and application framework for building software.

For more details please go to  LatticeMico System Development Tools
 

Supported Development Boards

Lattice has pre-defined a number of its development boards as platforms within the LatticeMico System Software.  This allows you to rapidly start developing LatticeMico32 based systems on these boards.  The following boards have been developed:

• LatticeMico32 Development Board for LatticeECP2
• LatticeMico32 Development Board for LatticeECP

LatticeMico32 Demonstrations

Lattice develops designs that demonstrate the use of the LatticeMico32 for a variety of system level applications.  The following demonstrations are currently supported.

• LatticeMico32 100Mbps Tri-Speed Ethernet MAC Demo

  This demonstrates 100Mbps operation of the Tri-Speed Ethernet MAC IP core on a LatticeMico32 Development Board for LatticeECP2 by using a web server in conjunction with the open-source Lightweight IP (lwIP) network stack.

• LatticeMico32 Gigabit Tri-Speed Ethernet MAC Demo

  This demonstrates the gigabit capability of the Tri-Speed Ethernet MAC IP core on a LatticeECP2 Advanced Board by using a web server in conjunction with the open-source Lightweight IP (lwIP) network stack.

• LatticeMico32 VGA and DDR SDRAM Demo

  This demo for the LatticeMico32 runs on a LatticeMico32 Development Board for LatticeECP2 and uses the DDR SDRAM Controller IP core.  The DRAM is partitioned and stores LatticeMico32 code in one section and VGA graphics information in another section.

   

Download and try it now

For the latest information of LatticeMico System Development Tools, go to the page located here. This page will always provide the latest release of LatticeMico System software.

For known issues related to LatticeMico32, please click here.