SPI4

In Detail

Release Notes

Documents & Downloads

User Manuals

Overview

The SPI4 Intellectual Property (IP) core enables user instantiation of OIF-compliant System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) cores in Lattice Field Programmable Gate Arrays (FPGAs). The SPI4 IP core supports up to 256 data channels with aggregate throughputs of between 3 and 12.8Gbps and can be used to connect network processors with OC192 framers, mappers, and fabrics, as well as Gigabit and 10-Gigabit Ethernet MACs.

SPI4.2 IP Core Block Diagram

Features

The Soft SPI4 IP core is fully compliant with the OIF System Packet Interface Level 4 Phase 2 Revision 1 (SPI4.2.1) interface standard
Supported through Diamond or ispLEVER IPexpress™ tool for easy user configuration and parameterization
Supports up to 256 independent channels
400 to 500MHz DDR Dynamic mode operation in LatticeSC and LatticeSCM devices
156 to 350MHz DDR Static timing mode operations for LatticeECP3 devices. Supports non-standard “SPI4 Lite” line rates.
Supports both 64b and 128b internal architectures for optimization of either speed or size
Requires only ~2000 slices (64b mode) for a full 256-channel Static mode core
Supports full bandwidth utilization of the SPI4 line in both directions - requires no idle cycles in the receive direction or insertion of idles in the transmit direction between bursts (as long as there is data available)
Parity error checking/generation on all receive and transmit control and data words (DIP4) and status (DIP2) interfaces
Parity error force capabilities on data (independent controls: control word and data) and status interfaces

Various run-time user controls
- Force idles (transmitter)
- Enable/disable packing (transmitter)
- Training pattern (CAL_M, MAX_T)
Complete run-time programmability of all internal FIFO thresholds for efficient management of SPI4 line in terms of Lmax and packing
Provides a direct interface to primary device I/O at the SPI4 interface and an internal FIFO interface to user logic
Supports minimum transmit burst sizes in increments of 16 bytes from 16 bytes up to 1008 bytes for optimized network processor applications
Support for packet sizes down to 4 bytes in length
Fully configurable 512-location calendar RAM for Rx and Tx directions and associated 256-location status RAMs
Two independently configurable methods of status reporting in the receive and transmit directions - RAM addressable and Transparent
Rising or falling edge selectable Status Channel I/O independently configurable in the receive and transmit directions

The SPI4 is a user-configurable IP core, which allows the configuration of the IP and generation of a netlist and simulation file for use in designs. Please note that generating a bitstream may be prevented or the bitstream may have time logic present unless a license for the IP is purchased.

Performance and Resource Utilization

LatticeECP3¹
Configuration		SLICEs	LUTs	REGs	I/Os	EBRs	Line Rate (MHz)
Bus Width	Status Mode	SLICEs	LUTs	REGs	I/Os	EBRs	Line Rate (MHz)
64	Transparent	2324	2600	3206	80	12	312
128	RAM	3967	4327	5185	80	18	350

1. Performance and utilization data are generated using an LFE3-70EA-8FN672CES device with Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance might vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeSC/M¹
Configuration		SLICEs	LUTs	REGs	I/Os	EBRs	Line Rate (MHz)
Bus Width	Status Mode	SLICEs	LUTs	REGs	I/Os	EBRs	Line Rate (MHz)
64	Transparent	2405	5126	3001	80	12	400
128	RAM	4015	5126	4840	80	18	400

1. Performance and utilization data are generated using an LFSC3GA25E-6FF1020C device with Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance might vary when using a different software version or targeting a different device density or speed grade within the LatticeSC/M family.

Ordering Information

Family

Part Numbers

LatticeECP3

SPI-42-E3-U3

LatticeSC/M

SPI-42-SC-U3

IP Version: 2.8
Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.
Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.