The RapidIO Interconnect Architecture is an industry-standard, packet-based interconnect technology that provides a reliable, high-performance interconnect between NPUs (network processing units), CPUs (central processing units), and DSPs (digital signal processors). Serial RapidIO enables chip-to-chip, board-to-board, and system-to-system communications and is targeted at the networking, embedded, and storage markets. RapidIO has won broad acceptance in wireless infrastructure applications, where it is used as a primary interconnect for DSP clusters in baseband processing.
Serial RapidIO Core Block Diagram
The figure above illustrates the overall architecture of the Serial RapidIO 2.1 Endpoint IP core. The Buffer/Mux module supports up to three ports for logical layer functions which simplifies connectivity when multiple local interfaces must be supported. The demultiplexing of incoming traffic to the LocaLink Rx ports is user defined. In addition to the RapidIO Physical layer functions, the core also includes Management Module that supports access to Physical, Transport, and Logical Layer CSRs either through maintenance transactions, or through the Alternate Management Interface (AMI). The Management Module also provides a soft packet interface that lets a processor send and receive software formatted RapidIO packets. This interface can be used for system level testing, or to implement logical layer functions in software saving valuable logic resources in FPGA applications.
| Configuration | Slices | LUTs | Registers | sysMEM EBRs | fMAX (MHz) |
|---|---|---|---|---|---|
| All Configurations | 10,694 | 15,981 | 9,859 | 10 | 1252 |
1. Performance and utilization data are generated using an LFE3-70EA-8FN672CES device with Lattice Diamond 1.0 and Synplify Pro D-2009.12L-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.
2. fMAX shown is for x4 operation at 2.5Gbaud using -8 speed grade devices.
| Family | Part Number |
| LatticeECP3 | SRIO-E3-U1 |
IP Version: 1.1
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LatticeECP3 AMC Demonstration Kit consists of
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