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The SYN1588®Clock_S IP-core provides highly accurate clock synchronization compliant to the IEEE 1588 standard version 1.0 and 2.0 for Industrial Ethernet applications. It provides a high resolution, high accuracy hardware clock which uses a 96-bit wide adder based clock architecture allowing supporting input clock frequencies in the range of 10 – 200 MHz. Furthermore the SYN1588 Clock_S comprises an MII-Scanner unit, which scans all Ethernet traffic in search for IEEE 1588 synchronization packets. Upon detection of any such packet it draws a 96-bit wide time stamp from the local clock and copies it together with status and identification data into a time-stamp FIFO.
This diagram shows the Syn1588 Clock_S IP Core highlighted in green and how it is connected into the communication system.

For a complete list of features, download the datasheet.
The following are typical performance and utilization results.
| Device | Speed grade | Slices | LUTs | REGs | EBRs | fMAX (MHz) |
|---|---|---|---|---|---|---|
|
XP |
-7 |
1668 |
1954 |
1726 |
4 |
75 |
|
XP2 |
-7 |
1552 |
1968 |
1591 |
4 |
125 |
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