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Closed Loop Power Supply Trimming

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Lattice Reference DesignsEnhanced closed-Loop trim expands the on-chip hardware trim engine by providing the ability to set trim targets in real-time through either an I2C or SPI serial interface, as well as the new feature of being able to select individual channels for trimming operations. In addition, this reference design provides the option of supporting up to two VID trim channels, where up to 16 distinct trim targets per supply can be dynamically selected through a 4-bit binary code.

Features

 

Platform Manager Closed Loop Trim Diagram Sml 

  

Tested Devices* FPGA
LUTs
FPGA
Slices
CPLD
Macrocells
CPLD
Product Terms
VMONs I/Os Timers HVOUTs Revision
LPTM10-12107 507 254 -  - (note 1.) 6  -  - 1.0

1. While this design reads VMON voltages, it does not prevent the VMON inputs from being used by the CPLD logic.
 


PDF file download design documentation (RD1078)

EXE files download source code

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

 

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