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Long Delay Timer Functions

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Lattice Reference DesignsThis reference design demontrates the techniques necessary for generating long duration timeouts. Timeouts of 2, 4 8 or 16 seconds are demonstrated. The code for performing these kind of timer functions is useful when implementing functions such as watchdog timers, or when monitoring a long or complicated sequence of events. 

This reference design is compatible with the Platform Manager Development Kit.

Features

 

Platform Manager Long Timers Diagram Sml

 

 

Tested Devices* FPGA
LUTs
FPGA
Slices
CPLD
Macrocells
CPLD
Product Terms
VMONs I/Os Timers HVOUTs Revision
LPTM10-12107 44  25 18   -  5  -  4  - 1.0

PDF file download design documentation (RD1079)

EXE files download source code

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.

 

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