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ispClock5300S

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The ispClock5300S (single-ended) is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution applications. The ispClock5300S family provides 4 to 20 single-ended ultra low skew outputs.

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ispClock5300S

Block Diagram

 

Applications 

  • Circuit board common clock distribution
  • PLL-based frequency generation
  • High fan-out clock buffer
  • Zero-delay clock buffer

 

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Features 

 

  • Four Operating Configurations
    • Zero delay buffer
    • Zero delay and non-zero delay buffer
    • Dual non-zero delay buffer
    • Non-zero delay buffer with output divider
  • 8MHz to 267MHz Input/Output Operation
  • Low Output to Output Skew (<100ps)
  • Low Jitter Peak-to-Peak (< 70 ps)
  • Up to 20 Programmable Fan-out Buffers
    • Programmable single-ended output standards and individual enable controls
      • LVTTL, LVCMOS, HSTL, eHSTL, SSTL
    • Programmable output impedance
      • 40 to 70Ω in 5Ω increments
    • Programmable slew rate
    • Up to 10 banks with individual VCCO and GND
      • 1.5V, 1.8V, 2.5V, 3.3V
  • Fully Integrated High-Performance PLL
    • Programmable lock detect
    • Three "Power of 2" output dividers (5-bit)
    • Programmable on-chip loop filter
    • Compatible with spread spectrum clocks
  • Precision Programmable Phase Adjustment (Skew) Per Output
  • 8 settings; minimum step size 156ps
    • Locked to VCO frequency
  
  • Up to +/- 5ns skew range
  • Coarse and fine adjustment modes
  • Up to Three Clock Frequency Domains
  • Flexible Clock Reference and External Feedback Inputs
    • Programmable single-ended or differential input reference standards
      • LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, Differential SSTL
    • Clock A/B selection multiplexer
    • Programmable Feedback Standards
      • LVTTL, LVCMOS, SSTL, HSTL
    • Programmable termination
  • All Inputs and Outputs are Hot Socket Compliant
  • Full JTAG Boundary Scan Test In-System Programming Support
  • Exceptional Power Supply Noise Immunity
  • Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
  • 48-pin and 64-pin TQFP Packages
  • Applications
    • Circuit board common clock distribution
    • PLL-based frequency generation
    • High fan-out clock buffer
    • Zero-delay clock buffer

Four Modes of Operation

 

Clock 5300S Zero Delay Buffer Mode

Zero Delay Buffer Mode
Clock5300S Dual Non-Zero Delay Buffer Mode

Dual Non-Zero Delay Buffer Mode
   
Clock5300S Zero and Non-Zero Delay Buffer Mode

Zero Delay Buffer and Non-Zero Delay Buffer Mode
clock5300S Non-Zero Delay Buffer w/ and w/o Divider

Non-Zero Delay Buffer with and without Output Dividers

 

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Selector Guide 

ispClock5300S Product Family Selector Guide
Feature  ispClock5300S Family
5320S 5316S 5312S 5308S 5304S
  22 pixel circular buy icon 22 pixel circular buy icon 22 pixel circular buy icon 22 pixel circular buy icon 22 pixel circular buy icon
 Outputs 20 16 12 8 4
 Input Operating Frequency Range 8 to 267MHz
 Output Operating Frequency Range 5 to 267MHz
 VCO Operation 160 to 400MHz
 Spread Spectrum Compatibility Yes
 Programmable Input Types LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL
 Programmable Output and
Feedback Interface Types		 LVTTL, LVCMOS, SSTL, HSTL
 Type of PLL Feedback External
 M, N Dividers None
 Number of V Dividers 3
 V Divider Count Range 1 to 32 (in powers of 2)
 Maximum Cycle-Cycle Jitter 70ps (peak-peak)
 Maximum Period Jitter (RMS) 12ps
 Maximum Phase Jitter (RMS) 50ps
 Maximum Static Phase Offset -40ps to 100ps
 Frequencies Generated 3
 Programmable Skew 156ps to 5ns
 Fan-out Buffer Mode Yes
 Programmable Termination 40 to 70Ω & 20Ω Setting

 

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