ispClock5600A

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The ispClock5610A and ispClock5620A are in-system-programmable high-fanout enhanced zero delay clock generators designed for use in high performance communications and computing applications. The ispClock5610A provides up to 10 single-ended or 5 differential clock outputs, while the ispClock5620A provides up to 20 single-ended or 10 differential clock outputs.

Applications
Features
Selector Guide

Please select a document category from the selection on the left-hand side of this page for more information on ispClock5600A.

Block Diagram

Applications

Generating and distributing multiple board clocks from a single source
Generates multiple frequencies
Supports multiple signaling logic interfaces
Compensates for trace length and loading differences
Improves signal integrity with trace length matching

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Features

8MHz to 400MHz Input/Output Operation
Low Output to Output Skew (<50ps)
Low Jitter Peak-to-Peak
Up to 20 Programmable Fan-out Buffers
- Programmable output standards and individual enable controls
  - LVTTL, LVCMOS, HSTL, eHSTL, SSTL, LVDS, LVPECL, Differential HSTL, SSTL
- Programmable output impedance
  - 40 to 70Ω in 5Ω increments
- Programmable slew rate
- Up to 10 banks with individual V_CCO and GND
  - 1.5V, 1.8V, 2.5V, 3.3V

Fully Integrated High-Performance PLL
- Programmable lock detect
- Multiply and divide ratio controlled by
  - Input divider (1 to 40)
  - Feedback divider (1 to 40)
  - Five output dividers (2 to 80 even multiples)
- Programmable on-chip loop filter
- Compatible with spread spectrum clocks
Precision Programmable Phase Adjustment (Skew) Per Output
- 16 settings; minimum step size 156ps
  - Locked to VCO frequency
- Up to +/- 12ns skew range
- Coarse and fine adjustment modes

Up to Five Clock Frequency Domains
Flexible Clock Reference and External Feedback Inputs
- Programmable input standards
  - LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Differential HSTL, SSTL
- Clock A/B selection multiplexer
- Feedback A/B selection multiplexer
- Programmable termination
All Inputs and Outputs are Hot Socket Compliant
Four User-programmable Profiles Stored in E²CMOS^® Memory
- Supports both test and multiple operating configurations
Full JTAG Boundary Scan Test In-System Programming Support
Exceptional Power Supply Noise Immunity
Commercial (0 to 70°C) and Industrial (-40 to 85°C) Temperature Ranges
100-pin and 48-pin TQFP Packages
Applications
- Circuit board common clock generation and distribution
- PLL-based frequency generation
- High fan-out clock buffer
- Zero-delay clock buffer

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Selector Guide

ispClock5600A Product Family Selector Guide
Feature	ispClock5600A Family
Feature	5620A	5610A

Outputs	20	10
Input Operating Frequency Range	8 to 400MHz
Output Operating Frequency Range	4 to 400MHz
VCO Operation	320 to 800MHz
Spread Spectrum Compatibility	Yes
Programmable Input Types	LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL
Programmable Output and Feedback Interface Types	LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, Diff. SSTL, Diff. HSTL
Type of PLL Feedback	Internal/External
M, N Dividers	Count from 1 to 40
Number of V Dividers	5
V Divider Count Range	2 to 80 (in steps of 2)
Maximum Cycle-Cycle Jitter	70ps (peak-peak)
Maximum Period Jitter (RMS)	12ps
Maximum Phase Jitter (RMS)	50ps
Maximum Static Phase Offset	-100ps to 200ps
Frequencies Generated	5
Programmable Skew	156ps to 12ns
Fan-out Buffer Mode	No
Programmable Termination	40 to 70Ω & 20Ω Setting

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