The LatticeXP FPGA devices utilize a combination of non-volatile FLASH cells and SRAM technology to deliver a single-chip solution supporting "instant-on" start-up and infinite re-configurability. A non-volatile FLASH cell array distributed within the LatticeXP FPGA device stores the device configuration. At power-up the configuration is transferred from FLASH memory to configuration SRAM in less than 1mS providing an instant-on FPGA. In addition, LatticeXP FPGA devices provide security by eliminating the need for an external configuration bit-stream and by providing non-volatile security features.
More of the Best: The LatticeXP gives you the features you expect from FPGAs plus on-chip flash memory, unique TransFR field update technology and a sleep mode for power conservation.
Non-volatile, reprogrammable FPGAs are well suited for implementing system logic in a wide variety of end markets including communications, consumer, industrial, computing, military and automotive. These are especially well suited where there is a requirement for instant-on, reduced parts count, high-security or real time programming.
Lattice offers two evaluation boards boards for the LatticeXP FPGA. These boards provide ready-made platforms for evaluating the features and performance of the LatticeXP, or aiding in the development of your design:
LatticeXP Standard Evaluation Board: This board is an efficient design featuring a 256-ball fpBGA FPGA device, on-board oscillator, SPI Flash configuration, on-board power control, prototyping area, various LEDs and more.
LatticeXP Advanced Evaluation Board: Designed for more advanced evaluation and development, this board includes all the features of the LatticeEC Standard Evaluation Board, plus a DDR memory interface, E-net PHY, on-board FCRAM, general purpose RJ-45 connector, additional power options, SMA connectors and more.
| View Datasheet |
LFXP3 | LFXP6 | LFXP10 | LFXP15 | LFXP20 |
|---|---|---|---|---|---|
| Vcc Voltage (V) | 1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
1.2 or 1.8/2.5/3.3 |
| PFU Rows | 16 | 24 | 32 | 40 | 44 |
| PFU Columns | 24 | 30 | 38 | 48 | 56 |
| # of PFUs | 384 | 720 | 1216 | 1932 | 2464 |
| LUTs (K) | 3.1 | 5.8 | 9.7 | 15.4 | 19.7 |
| Dist. RAM (K bits) | 12 | 23 | 39 | 61 | 79 |
| EBR SRAM (K bits) | 54 | 72 | 216 | 324 | 396 |
| # of EBR SRAM Blocks | 6 | 8 | 24 | 36 | 44 |
| PLLs | 2 | 2 | 4 | 4 | 4 |
| Maximum User I/O | 136 | 188 | 244 | 300 | 340 |
| Packages | I /O Count |
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| 100-pin TQFP (14x14 mm) | 62![]() |
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| 144-pin TQFP (20x20 mm) | 100![]() |
100![]() |
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| 208-pin PQFP (28x28 mm) | 136![]() |
142![]() |
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| 256-ball fpBGA (17x17 mm) | 188![]() |
188![]() |
188![]() |
188![]() |
|
| 388-ball fpBGA (23x23 mm) | 244![]() |
268![]() |
268![]() |
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| 484-ball fpBGA (23x23 mm) | 300![]() |
340![]() |
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