The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for automotive applications traditionally implemented using CPLDs or low-capacity FPGAs. Widely adopted in a broad range of applications that require general purpose I/O expansion, interface bridging and power-up management functions, MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFRTM technology) and a low power sleep mode, all in a single-device.
| 256E/C | 640E/C | 1200E | 2280E | |
|---|---|---|---|---|
| Vcc Voltage (V) | 1.2 and 1.8/2.5/3.3 |
1.2 and 1.8/2.5/3.3 |
1.2 | 1.2 |
| Density LUTs | 256 | 640 | 1200 | 2280 |
| Density Macrocells1 | 128 | 320 | 600 | 1140 |
| tPD (ns) | 4.9 | 4.9 | 5.1 | 5.1 |
| Fmax (MHz) | 277 | 277 | 277 | 277 |
| Dist. RAM (Kbits) | 2.0 | 6.0 | 6.25 | 7.5 |
| EBR SRAM (Kbits) | 0 | 0 | 9.2 | 27.6 |
| EBR SRAM Blocks | 0 | 0 | 1 | 3 |
| PLLs | 0 | 0 | 1 | 2 |
| Maximum User I/O | 78 | 159 | 211 | 271 |
| Packaging | ||||
| 100-pin TQFP (14x14 mm) | 78 | 74 | 73 | 73 |
| 144-pin TQFP (20x20 mm) | 113 | 113 | 113 | |
| 256-ball ftBGA (17x17 mm) | 159 | 211 | 211 | |
| 324-ball ftBGA (19x19 mm) | 271 | |||
1 Assumes 1 macrocell = 2 LUTs
© Lattice Semiconductor Corporation 2012
