The LatticeXP2 devices combine a Look-up Table (LUT) based FPGA fabric with Flash Non-volatile cells in an architecture referred to as flexiFLASH. The flexiFLASH approach provides benefits such as instant-on, small footprint, on chip storage with FlashBAK embedded block memories and Serial TAG memory and design security. The parts also support Live Updates with TransFR, 128-bit AES Encryption and Dual-Boot technologies. The LatticeXP2 FPGA fabric utilizes an underlying LatticeECP2 architecture that was optimized from the outset with high performance and low cost in mind. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP blocks.
| Device | LA-XP2-5 | LA-XP2-8 | LA-XP2-17 | ||||
|---|---|---|---|---|---|---|---|
| LUTs (K) | 5 | 8 | 17 | ||||
| Distributed RAM (Kbits) | 10 | 18 | 35 | ||||
| EBR SRAM (Kbits) | 166 | 221 | 276 | ||||
| EBR SRAM Blocks | 9 | 12 | 15 | ||||
| sysDSP Blocks | 3 | 4 | 5 | ||||
| 18x18 Multipliers | 12 | 16 | 20 | ||||
| PLL | 2 | 2 | 4 | ||||
| Maximum Available I/O | 172 | 201 | 201 | ||||
| Packages | I/O Count | ||||||
| 132-pin csBGA (8 x 8 mm) | 86 | 86 | |||||
| 144-pin TQFP (20 x 20 mm) | 100 | 100 | |||||
| 208-pin PQFP (28 x 28 mm) | 146 | 146 | 146 | ||||
| 256-ball ftBGA (17 x 17 mm) | 172 | 201 | 201 | ||||