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Memory Interfaces

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Lattice provides a wide range of high-performance interface solutions for the latest memory technologies. These solutions combine innovative silicon with Intellectual Property (IP) cores to provide robust solutions for networking applications.

Features

  • LatticeSC FPGA devices provide full-featured embedded high-speed memory controllers supporting DDRI/II SDRAM, QDR I/II SRAM, and RLDRAM I/II memory devices.
  • LatticeECP3/ECP2/M/ECP/XP2/XP FPGA devices provide dedicated resources to align DQ and DQS signals, multiplex/de-multiplex to and from double data rate, and transfer data from the DQS clock domain to the system clock domain.
  • LatticeECP3 devices provide support for DDR3 Read and Write leveling to adjust for PCB route delay on read and write data transfers.
  • Lattice ORSPI4 FPSC contains an embedded QDR II memory interface providing 20+ Gbps bandwidth w/simple FIFO interface to FPGA.
  • Through the ispLeverCORE program, Lattice offers a variety of IP cores and Reference Designs for popular memory interfaces.
Memory Interface Standards, IP and Reference Designs
Memory Standard I/O Standard Max Clock Rate Data Rate Hard IP Soft IP Reference Designs
DDR SDRAM SSTL 2.5V 200 MHz1 400 Mbps2 LatticeSC DDR/DDR2 SDRAM MACO Controller
 DDR SDRAM Controller - Pipelined/Non-Pipelined DDR SDRAM Controller
DDR2 SDRAM SSTL 1.8V 333 MHz1 667 Mbps2 LatticeSC DDR/DDR2 SDRAM MACO Controller DDR2 SDRAM Controller - Pipelined
  
DDR3 SDRAM  SSTL 1.5V
 400 MHz3 800 Mbps   Coming Soon
  
QDR I/II/II+ SRAM
 HSTL 1.8V or 1.5V 350 MHz 700 Mbps LatticeSC QDR MACO Controller
   QDR Memory Controller
RLDRAM I/II HSTL 1.8V 800 Mbps 400 MHz LatticeSC RLDRAM MACO Controller
    
1 For LatticeXP2, Clock Frequency for DDR1/2 SDRAM is 200 MHz, Pin Throughput of 400 Mbps
2 For LatticeXP, Clock Frequency for DDR1/2 SDRAM is 166 MHz, Pin Throughput of 333 Mbps
3 Supported in LatticeECP3 family

Read more:

Lattice supports the following memory vendors

Micron, Inc. www.micron.com Micron Logo
Qimonda www.qimonda.com Qimonda
Samsung www.samsung.com Samsung Logo

Memory in Networking Applications

Large, fast memory devices are required in networking and communications applications, with tasks ranging from simple address lookups to traffic shaping/policing to buffer management. Figure 1 illustrates a typical networking architecture. At 10 Gbps, address lookups with a typical read-to-write ratio of 1000:1 could easily be handled with Double Data Rate (DDR) SRAM. Link list management, traffic shaping and statistics gathering tasks typically have a balanced 1:1 read-to-write ratio, requiring higher-performance Quad Data Rate (QDR) SRAM. On the other hand, larger buffer memories are typically implemented in DDR SDRAMs (Synchronous DRAMs). A replacement for DRAM, SDRAM synchronizes memory access with a processor clock for faster data transfer.

Figure 1: Memory in a typical networking application

Memory diagram

Another popular memory devive for high-performance applications is RLDRAM. Reduced Latency DRAM (RLDRAM) provides SRAM-type interface, non-multiplexed addresses. RLDRAM technology provides minimized latency and reduced row cycle times that are well suited for applications requiring critical response time and very fast random accesses, such as next generation (10 Gbps and beyond) networking applications.