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FPGA
    LatticeECP3 FPGA
    LatticeXP2 FPGA
Intellectual Property - Lattice IP Cores and Reference Designs
    Lattice IP Cores
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FPGA

  • LatticeECP3 FPGA
  • Sub-LVDS Signaling Using Lattice Devices [PDF, 312]
    UPDATED 2010-07-28 17:01:37.0 - TN1210 - Sub-LVDS Signaling Using Lattice Devices. This is an initial release of the technical note demonstrating how sub-LVDS signaling can be implemented using existing LatticeECP3 and LatticeXP2 I/O standard support.
  • SERDES
  • LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability [PDF, 1437]
    NEW 2010-07-26 10:47:09.0 - This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a LatticeECP3™ device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer (up to the MAC client interface) of the 10-Gigabit Ethernet protocol stack on the LatticeECP3 device. Specifically, the document discusses the following topics: " Overview of LatticeECP3™ devices and Marvell Alaska 88X2040 devices " Physical/MAC layer interoperability setup, testing, and results
  • Eval Boards & Demos
  • XAUI Demo
  • LatticeECP3 XAUI Demo [ZIP, 1618]
    UPDATED 2010-07-22 12:57:50.0 - Updated
  • LatticeXP2 FPGA
  • Sub-LVDS Signaling Using Lattice Devices [PDF, 312]
    UPDATED 2010-07-28 17:01:37.0 - TN1210 - Sub-LVDS Signaling Using Lattice Devices. This is an initial release of the technical note demonstrating how sub-LVDS signaling can be implemented using existing LatticeECP3 and LatticeXP2 I/O standard support.

    • Intellectual Property - Lattice IP Cores and Reference Designs

  • Lattice IP Cores
  • 32 Bit PCI Target
  • PCI Core IP User's Guide [PDF, 4718]
    UPDATED 2010-07-23 13:22:44.0 - Updated document format. Added new content in chapters 1 & 4
  • 64 Bit PCI Target
  • PCI Core IP User's Guide [PDF, 4718]
    UPDATED 2010-07-23 13:22:44.0 - Updated document format. Added new content in chapters 1 & 4
  • 32 Bit PCI Master/Target
  • PCI Core IP User's Guide [PDF, 4718]
    UPDATED 2010-07-23 13:22:44.0 - Updated document format. Added new content in chapters 1 & 4
  • 64 Bit PCI Master/Target
  • PCI Core IP User's Guide [PDF, 4718]
    UPDATED 2010-07-23 13:22:44.0 - Updated document format. Added new content in chapters 1 & 4
  • 10Gb+ Ethernet MAC
  • LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability [PDF, 1437]
    NEW 2010-07-26 10:47:09.0 - This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a LatticeECP3™ device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer (up to the MAC client interface) of the 10-Gigabit Ethernet protocol stack on the LatticeECP3 device. Specifically, the document discusses the following topics: " Overview of LatticeECP3™ devices and Marvell Alaska 88X2040 devices " Physical/MAC layer interoperability setup, testing, and results
  • XAUI
  • LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability [PDF, 1437]
    NEW 2010-07-26 10:47:09.0 - This technical note describes a Physical/MAC Layer 10-Gigabit Ethernet interoperability test between a LatticeECP3™ device and the Marvell Alaska 88X2040 device. The test exercises the Physical/MAC Layer (up to the MAC client interface) of the 10-Gigabit Ethernet protocol stack on the LatticeECP3 device. Specifically, the document discusses the following topics: " Overview of LatticeECP3™ devices and Marvell Alaska 88X2040 devices " Physical/MAC layer interoperability setup, testing, and results
  • SGMII and Gb Ethernet PCS
  • LatticeECP3 and Broadcom 1 GbE (1000BASE-X) Physical/MAC Layer Interoperability [PDF, 1498]
    NEW 2010-07-26 10:35:44.0 - This technical note describes a 1000BASE-X physical/MAC layer Gigabit Ethernet interoperability test between a LatticeECP3™ device and the Broadcom BCM56800 network switch. Specifically, the document discusses the following topics: " Overview of LatticeECP3 devices and Broadcom BCM56800 network switch " 1000BASE-X physical/MAC layer interoperability setup and results